Mathcad Calculates Input Capacit

Abstract: Step-down buck regulators are extremely popular in a variety of portable and non-portable equipment. These buck converters are terminated with an input capacitor, C_IN and an output capacitor, C_O, at the output. C_IN provides high-frequency filtering, so that V_IN has low ripple. This application note helps a system designer to set-up Mathcad and compute C_IN for a particular step-down DC-DC regulator design.

Step-down buck regulators are used in portable and non-portable equipment, such as PDAs, cell phones, computers, telcom/networks, and consumer products. These buck converters are terminated with an input capacitor, C_IN, at the input, and an output capacitor, C_O, at the output. The function of both capacitors is to provide high-frequency filtering, so that V_IN and V_O are close to pure DC, with little ripple noise.

A capacitor is often represented by a series combination of R, L, and C. R is the equivalent series resistance (ESR) and L is the equivalent series inductance (ESL). The term C is equal to the ideal capacitor value.

Figure 1 shows a typical schematic of a synchronous buck power stage and the associated waveforms to be used for the derivations and calculations.

Figure 1. Typical synchronous buck power and waveforms.

Figure 1. Typical synchronous buck power and waveforms.

Setting up variables and data for example calculation in MathCad:

| Input Voltage | V_I := 12 | n := 10^-9 |
| Output Voltage | V_O := 3.3 | u := 10^-6, k := 10³ |
| Output Current | I_O := 25 | m := 10^-3 |
| High-Side Switch Drop | V_HS := 0.227 | |
| Low-Side Switch Drop | V_LS := 0.113 | |
| Switching Current Rise Time | T_RS := 25 × n | |
| Switching Current Fall Time | T_FS := 25 × n | |
| Switching Frequency | F_S := 600 × k | |
| Duty Cycle | D := (V_O + V_LS) / (V_I - V_HS + V_LS) | D = 0.287 |
| Switch(Q1) On Time | T_ON := D / F_S | |
| Switch(Q1) Off Time | T_OFF := 1 / F_S - T_ON | |
| Converter Efficiency | η := 0.9 | |
| Input Current | I_IN := V_O × I_O / η × V_I | I_IN := 7.639 |
| Output Inductor Pk-Pk Ripple Current |
I_RPL := 0.3 × I_O | |
| Input Capacitor | C_IN := 40 × u | (4 x 10uF ceramic of ESR = 10mΩ each and ESL = 2.5nH each) |
| Input Capacitor ESR | ESR_CIN := 2.5 × m | |
| Input Capacitor ESL | ESL_CIN := 0.625 × n | |

As seen in Figure 1, the output ripple current through the input capacitor results in voltage across C_IN that reflects the values of ESR, ESL, and C. The ESR and ESL cause fast step voltage rise and fall, whereas C has a linear voltage rise and fall due to the fact that the capacitor charges and discharges. At the start of T_ON, C_IN sees a negative step current, which will produce a negative step voltage given by the following equation:

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During T_ON, the capacitor discharges an average current of (I_O-I_IN), which causes a linear ΔV of:

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The total voltage deviation from the start of T_ON to the end of T_ON is the summation of the above:

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Similarly, but with opposite polarity, at the start of T_OFF and during T_OFF, the following voltage deviations are calculated:

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The peak-to-peak ripple is equal to the higher of the two, which is ΔVOFF~1V. As seen from the above, most of the ripple is caused by ESL and the fast di/dt. Di/dt of 1A/nS is very realistic in today's MHz DC-DC converters. Therefore, to reduce the ripple, more capacitors would need to be placed in parallel. Lower value ceramic capacitors, such as 0.1uF in the 0805 or 1206 package, have half the ESL of the 10uF, or ~1.2nH. Place the 0.1uF as close as possible to the sensitive decoupling points.

Another parameter that needs to be determined is the RMS current through the input capacitor, so that the capacitor I_RMS rating is not exceeded. From the I_CIN waveform, the RMS current can be approximated (since the peak-to-peak inductor ripple current is usually 20-30% of I_O max) to be:

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Where D = (V_O + V_LS) / (V_IN + V_LS + V_HS), and I_IN = (V_O × I_O) / η × V_IN

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To simplify further, let D = V_O/V_IN (since V₀ >> V_LS, and V_IN + V_LS - V_HS ~ V_IN), and I_IN = V_O × I_O/V_IN (since efficiency η ~ 1), so that the I_CINRMS equation above becomes:

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The simplified version produces only ~1.4% error, and involves only three known parameters: V_I, V_O, and I_O. V_O is fixed, and I_O, V_I can have a specified range, depending on the application. However, I_CINRMS always has a maximum value of I_O/2, which happens at V_I = 2V_O, and decreases the value for V_I < 2I_O and V_I > 2L_O. The plot in Figure 2 below illustrates this:

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Figure 2.

Figure 2.

Due to the high di/dt and pulsating current, a ceramic capacitor is chosen, for its low ESR and ESL. A higher ripple current rating is required at high-frequency to contain the switching spikes. Make sure the RMS current rating of the capacitor is well above the maximum operating RMS current. For long-term reliability, choose a capacitor that will exhibit less than a 10°C temperature rise. Most capacitor manufacturers provide plots that show RMS current vs. temperature rise.