英伟达NVIDIA | 社招 深度学习架构/CPU设计/资深验证
NVIDIA上海办公室，作为NVIDIA全球核心的研发中心之一，现开放芯片类社招职位如下，有兴趣的朋友欢迎通过发送邮件至heatherl@nvidia.com与我们联络。
架构类
Senior NVDLA (Deep Learning Accelerate) Architecture Engineer
Senior CPU Architecture Engineer (RISC-V)
Senior Display Architecture Engineer
设计类
ASIC Design Engineer (Clock)
SOC Design Engineer
ASIC Design Engineer (DFT Mbist)
验证类
Senior Verification Engineer
ASIC Design/Verification Engineer
ASIC Verification Engineer (ATE)
后端类
DFT Engineer
ASIC PD Engineer
ASIC PD Methodology Engineer
Senior Physical Design Engineer
Senior NVDLA Architecture Engineer
工作职责
1. Building next generation of NVDLA for both internal usage and open source
2. Work on Deep-Learning architecture, algorithms, and software development
3. Develop function/performance/power models for NVDLA
4. Co-work with other HW team to deliver high quality Deep-Learning processors.
任职资格
1. MS/Ph.D in electrical/computer engineering and related.
2. 3+ years strong experience in algorithm/architecture development in one or some of the following technologies: CPU, GPU, DSP, deep-learning processor, Image Processor.
3. Solid software skills in C/C++
加分项
1. Hardware design or driver development background is a plus.
2. Fluent English (both written and spoken) and excellent communication skills
3. Demonstrated ability to work independently as well as in a multi-disciplinary group environment
Senior CPU Architecture Engineer (RISC-V)
工作职责
1. Architect NVIDIA's next generation of RISCV CPU
2. Co-work with software team to identify architecture requirements
3. Evaluation of different architecture solutions
4. Define architecture of the CPU core and various hardware components surrounding the CPU, like local memory, interconnect and crypto accelerators
5. Validate the new architecture on CMOD
任职资格
1. BS/MS in electrical/computer engineering and related.
2. 3+ years’ experience in hardware architecture
3. Strong skills in C/C++
4. Solid understanding to computer architecture
加分项
1. Project experiences of complex CPU architecture
2. Knowledge or project experiences of RISCV CPU
3. Knowledge of project experiences on SystemC modeling
4. Broad understanding to computer security and crypro algorithms like AES/SHA/RSA/ECC
5. Fluent English (both written and spoken) and excellent communication skills
6. Demonstrated ability to work independently as well as in a multi-disciplinary group environment
Senior Display Architecture Engineer
工作职责
1. Building next generation of unified Display for both Tegra and GPU
2. Learn display HW/SW programming model and write internal architecture spec
3. Develop function models for unified display
4. Develop validation testplan and tests for function model
5. Co-work with ASIC/Verif/SW group to do full display and full chip verification
任职资格
1. MS/Ph.D in electrical/computer engineering and related.
2. 3+ years strong experience in algorithm/architecture development in one or some of the following technologies: Image Processor, video processor, display engine
3. Solid software skills in C/C++
加分项
1. Experienced with Perl & systemC, pixel processing background is a plus.
2. Fluent English (both written and spoken) and excellent communication skills
3. Demonstrated ability to work independently as well as in a multi-disciplinary group environment
ASIC Design Engineer (Clock)
The NVIDIA SOC Clock group is now looking for ASIC engineers with strong logic design background. In this position, you will take part in all stages to design modern complex GPU chips with state-of-art features and flows. To implement various functions, you will work directly with different global teams, as ARCH/SW, ASIC Design, CAD, Package, DFT and Physical Design teams. Additionally, you will be involved in defining and creating methodologies that create more efficient and flexible SOCs in future.
工作职责
1. Chip top integration and assembling, design quality checks
2. Module-level or Chip-level logic design, synthesis, timing constraints
3. Chip-level validation, both for function and test mode
4. Methodology or Flow development for above tasks.
任职资格
1. BS / MS in electrical / computer engineering and related.
2. Understand ASIC design and implementation flow
3. Familiar with design/verification languages as Verilog/VHDL, C/C++
4. Know industrial standard scripting language as Perl or Python
加分项
1. Excellent analytical and problem-solving skills
2. Fluent English and excellent communication skills
3. Good team work spirit, easy to cooperate with team members
4. Experience in RTL build and design automation is a plus
5. Understand JTAG or DFT is a plus
SOC Design Engineer
工作职责
1. Responsible for creating complex GPUs and SOCs and interface directly with unit-level, Physical Design, CAD, Package Design, Software, DFT and other teams
2. Get involved with defining and creating methodologies that create more efficient and flexible SOCs in future.
任职资格
1. BS or MS (preferred) in EE or CS
2. Understand frontend ASIC design/verification/implementation flow
3. Excellent analytical and problem-solving skills
4. Strong coding skills in Perl or other industry-standard scripting languages
5. Fluent English (both written and spoken) and excellent communication skills to interface with many groups and build consensus
6. Good team work spirit, easy to cooperate with team members
加分项
1. Prior experience in implementing System-On-Chip is a plus
2. Prior experience in RTL build and design automation is a plus
ASIC Design Engineer (DFT Mbist)
工作职责
You'll be responsible for MBIST (Memory BIST) implementation in RTL in near term.
1. Work closely with functional designers and SOC integration team to get MBIST implemented in RTL
2. Make sure MBIST logic go through verifications correctly
3. Fix MBIST timing or physical implementation issues based on Timing and PnR team's feedback
4. Help to improve MBIST design or implementation flow continuously
In long term, you'll be owning DFT design and methodology work or extend the expertise to other DFT areas.
任职资格
1. BSEE with 3+, MSEE with 2+ years of experience or PhD in DFT or ASIC design.
2. Solid background on Verilog and RTL coding
3. DFT experience on one or more areas is a plus, such as MBIST, boundary scan, 1500, Scan, ATPG
4. Good exposure to SOC integration, timing/STA, place-n-route or power is a plus
5. Excellent analytical skills in verification
6. Strong programming and scripting skills in Perl, Python or Tcl desired
7. Excellent written and oral communication skills in English with the curiosity to work on challenges
Senior Verification Engineer
工作职责
1. You will participate in the research of verification methodology to improve automation and productivity to produce Nvidia’s new high-quality state of the art products.
2. Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.
3. You responses to build block/IP testbench based on UVM methodology.
4. The responsibilities includes building test run and regression flow. Triage failures in regression and help designer root cause the bug.
5. Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health.
6. Take SOC verification on fullchip test environment for IPs
7. Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.
8. Deploy the advanced verification methodology and infrastructure of the SOC/IP
任职资格
1. BS / MS in electrical / computer engineering and related.
2. 3+ years (MS) or 5+ years (BS) working experience.
3. Familiar with advance verification methodology (UVM, VMM, OVM, etc), tools and flow
4. Fully experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling.
5. Deep understanding in Verilog and HVL (High-level Verification Language)
加分项
1. Strong programming skills in Perl and C/C++is plus
2. Having good arch/design experience is big plus.
3. At least good at one of the script programing lanange : Perl, Shell, Ruby, Python, etc.
4. Fluent English (both written and spoken) and excellent communication skills
5. Proven ability to work independently as well as in a multi-disciplinary group environment
6. Strong analytical skills
ASIC Design/Verification Engineer
工作职责
1. Micro-architecture definition for System-level modules (Reset, Fuse, Strap, In-silicon measurement, Floorsweep, etc…)
2. RTL design, synthesis, timing and silicon bring-up
3. Unit-level and System-level verification
4. Chip level integration
任职资格
1. BS / MS in electrical / computer engineering and related.
2. Familiar with verification methodology, tools and flow
3. Understand frontend ASIC design flow including RTL design, synthesis and timing analysis
4. Excellent analytical and problem-solving skills
5. Broad knowledge with Video techniques, SOC architecture and Computer architecture is a big plus
6. Strong programming skills in C/C++ and Perl is appreciated as a plus
7. Fluent English (both written and spoken) and excellent communication skills
8. Good team work spirit, easy to cooperate with team members
ASIC Verification Engineer (ATE)
工作职责
1. You'll be responsible for DFT verification environment setup, own verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, etc. You'll have chance to take the lead role for all ATE verifications and bringup.
2. In long term, you can be DFT lead for verification or extend the expertise to DFT design or implementation.
任职资格
1. BSEE with 3+, MSEE with 2+ years of experience or PhD in DFT or design verification
2. Good understanding on ASIC design and verification
3. Hands on experience on at least one DFT feature: Boundary Scan, 1500, MBIST, Scan, ATPG
4. Experience in silicon debug and bring-up on the ATE is a plus
5. Good exposure to clock design, timing/STA, place-n-route or power is a plus
6. Excellent analytical skills in verification and debug
7. Strong programming and scripting skills in Perl, Python or Tcl desired
8. Excellent written and oral communication skills in English with the curiosity to work on challenges
DFT Engineer
Shanghai power team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies for power optimization. We want to hire promising talent who can handle project(s) individually/collectively and add new dimension to the team.
工作职责
1. You'll be responsible for DFT planning, DFT implementation, DFT verification and silicon bring up at IP or fullchip level for all of NVIDIA's semiconductor products, starting with Memory BIST design and implementation.
2. In addition, you will have chance to improve DFT design, architecture and flow continuously.
任职资格
1. BSEE with 3+, MSEE with 2+ years of experience or PhD in DFT or related domains.
2. Solid background on Verilog and ASIC design
3. Proven knowledge and expertise in defining and implementing 1500, Scan test plans and ATPG
4. Deep understanding on Memory BIST
5. Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
6. Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
7. Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing and diagnostics
8. Strong programming and scripting skills in Perl, Python or Tcl desired
9. Excellent written and oral communication skills in English with the curiosity to work on rare challenges
ASIC PD Engineer
工作职责
1. Chip integration and netlist generation
2. Synthesis
3. Netlist quality check
4. Formal Verification
5. Constraints creation and validation, timing budget.
6. Co-work with PR engineers to implement chip partition and floorplan
7. Work in conjunction with RR engineers to achieve timing closure for both partition and full chip level
8. Achieve special timing closure, such as io, test, clock etc.
9. Function eco creation
10. Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout)
11. Flow automation development
12. Methodology in any of above areas.
任职资格
1. BSEE, MSEE is preferred
2. Project experience in IC design implementation
3. Courses taken in circuit design, digital design
4. Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) is preferred
5. Ways to stand out from the crowd:
6. Proficient user of Perl or TCL is preferred
7. Excellent English communication skill
ASIC PD Methodology Engineer
工作职责
Responsible for the development of timing analysis and closuremethodologies and flow automation for large and high speed semicustom chipsusing deep submicron processes. This includes evaluating and helping improvecommercial timing signoff tools, developing internal tools and solutions, andsupporting the physical design implementation team to achieve speed of lighttiming closure.
任职资格
1. BS in Electrical or ComputerEngineering, MS preferred
2. 3+ years of experience inphysical design implementation of deep submicron digital ASIC.
3. Prior experience insynthesis, timing constraints, timing analysis and timing closure.
4. Power user of commercial STAtools such as Synopsys Prime Time or Cadence ETS
5. Solid knowledge about STAand timing signoff
6. Proficiency experience inPerl, TCL, Python or C++.
7. Good communication skills
8. Flow development orautomation experience in ASIC backend design is preferred
Senior Physical Design Engineer
工作职责
A senior role in physical design for NVIDIA GPU and Mobile chips Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.
任职资格
1. BS in Engineering or Science
2. Power user of EDA tools from Synopsys (ICC/DC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus) or Mentor (Olympus-SOC)
3. Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes
4. 3+ years of experience in above areas
加分项
1. MS in Engineering or Science
2. Knowledge in FinFET technology, circuit design, and package design
3. Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre)
4. Proficiency in Perl, Python, TCL and Makefile scripts
