数字集成电路:电路、系统分析与设计

ECE530 Homework 2 (Register Tran

2021-03-20  本文已影响0人  家琛的水笔

4.1 Original DC_EX power estimation

Power (mW) Original Design
Total Dynamic 3.0806
Cell Leakage .1141531
TOTAL 3.1947531
Area 18566.915742
Slack 7.08

4.2 Automatic Clock Gating Insertion

Power (mW) Original Design
Total Dynamic 2.3668
Cell Leakage .1168189
TOTAL 2.4836189
Area 16310.052098
Slack 7.81

4.3 Customized Clock Gating

Power (mW) Customized Clock Gating
Total Dynamic 2.3901
Cell Leakage .1164926
TOTAL 2.5065926
Area 16108.722405
Slack 7.27

4.4

Power (mW) CCG_1Bit__DC_EX_gen
Total Dynamic 3.0794
Cell Leakage .1273181
TOTAL 3.20671
Area 18699.25834
Slack 7.19
Power (mW) CCG_8Bit__DC_EX_gen
Total Dynamic 3.1719
Cell Leakage .1248888
TOTAL 3.2967888
Area 18507.314649
Slack 7.38
Power (mW) CCG_32Bit__DC_EX_gen
Total Dynamic 2.3885
Cell Leakage .1173696
TOTAL 2.5058696
Area 18566.915742
Slack 8.41
Power (mW) CCG_FINAL__DC_EX_gen
Total Dynamic 2.3582
Cell Leakage .1183295
TOTAL 2.4765295
Area 16662.496388
Slack 8.55
Power(mW) Original 1-Bit 8-Bit 32-Bit Customized Final (1-Bit and 32-Bit)Total

参考:530HW2.docx - ECE 530 HW2 4.1 Original DC_EX power...

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