Verilog常用算法-以2为求对数

文件名 log2.vh

    // log2 constant function
    function integer log2(input integer x);
        integer i;
        begin
            i = 1;
            while (2**i < x)
            begin
                i = i + 1;
            end
            log2 = i;
        end
    endfunction

定义localparam N=log2(10);即令N=4

log2(2)等于1
log2(4)等于2
log2(16)等于4

50MHz频率一秒产生50,000,000个时钟计数，log2(50_000_000)等于26,需要26位计数器