用VHDL编写任意占空比方波信号输出

一个比较实用的小程序，在很多地方可以用到，实测可用。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity reseter is
port(clk:in std_logic;               --输入时钟100Mhz
     reset_out:buffer std_logic:='1');   --初始设为高电平
      end reseter;

architecture behav of reseter is
signal COUNT1 :INTEGER RANGE 0 TO 300000000:=0; 
signal count2 :integer range 0 to 300000000:=0;
begin

PROCESS(clk,reset_out) 
 
BEGIN 
IF RISING_EDGE(clk) THEN
IF reset_out='1' THEN                           --1S高电平
    IF COUNT1=1000000 THEN 
     --IF COUNT1=40 THEN 
     reset_out<='0'; COUNT1<=0; 
    ELSE COUNT1<=count1+1;  
  END IF; 
ELSE
     if count2=200000000 then                 --2S低电平
     -- if count2=300 then
      reset_out<='1'; count2<=0;
      else count2<=count2+1;
END IF;
end if;
end if;
END PROCESS ;
end behav;